Overview TSMC (TSM) is currently widely seen as the leader in semiconductor technology. However, this is not something it achieved by doing anything noteworthy: TSMC inherited this status from Intel (INTC) as the latter took five years to launch its first 10nm product, whereas Moore’s Law calls for a two-year cadence. TSMC did nothing but continue to adhere to said cadence.
Indeed, in an article early this year (and that admittedly has become outdated since Intel announced its 7nm delay), I already noted that TSMC itself was not particularly moving fast, also falling behind the Moore’s Law curve: TSMC was transitioning from 5nm (N5) to 3nm (N3) on a longer-than-usual 2.5-year cadence, while also increasing density by much less than the 2.0x Moore’s Law calls for: for example, SRAM density will only improve by a meager 1.2x. (So at the time, I noted that this gave Intel an opportunity to catch up, but Intel subsequently delayed its 7nm, which previously was intended to allow Intel to move on quickly from its plagued 10nm node.)
Recently, the first report about 2nm (N2) has arrived. As expected, this will mark TSMC’s transition from the FinFET transistor, first introduced by Intel in 2012 before being adopted by TSMC in 2015, to the gate-all-around transistor or GAAFET. Notably, TSMC is slated to move back to 2-year cadence, which implies an early 2025 market introduction of N2, after a decade of FinFET.
The issue with this is that TSMC’s two remaining leading edge competitors, Samsung and Intel, are both scheduled to move to the GAAFET ahead of TSMC. This means that TSMC could go from first to third by 2024.
For investors, that means they should not assume TSMC is the last foundry standing to pursue Moore’s Law, as competition is set to intensify.
對於投資者來說，這意味著他們不應該認為台積電是追求摩爾定律的最後一家半導體工廠 ，因為競爭將加劇。
Terminology I use GAAFET (gate-all-around) as the general term for a transistor whose gate surrounds all four sides of the channel. A FinFET surrounds three sides, and a planar one only one side.
Samsung mostly uses the term MCBFET (multi-channel bridge) or nanosheet.
三星通常使用術語MCBFET或nanosheet。
Samsung differentiates this from a nanowire, which as the name suggests is more like a wire than sheet of paper, in terms of geometry.
三星將其與nanowire區分開來，顧名思義，nanowire就幾何而言更像是線而不是紙。
A last name, mostly used by Intel, is nanoribbon. From the pictures from Intel's research, this seems similar to a nanosheet, but perhaps it is a bit in between both.
Lastly, node names: TSMC uses Nx, while Samsung and Intel continue to use xnm.
最後，節點名稱：TSMC使用Nx，而Samsung和Intel繼續使用xnm。
TSMC: N5, N3, N2 As widely known, TSMC has moved to N5 in the second half of 2020, at a two-year cadence compared to N7. However, initial findings suggest that while the cadence is on par with Moore’s Law, the shrink is not. In particular, the Apple (AAPL) A14 only achieved a density of 134MT (133 million transistor per mm2). This represent an increase of just 49% compared to 90MT on the A13.
This compares to TSMC’s claim of a 1.8x shrink with N5, which would result in a standardized density of 170MT. This lower shrink achieved by Apple can be attributed for a large part due to the much lower SRAM (memory) shrink of just 1.3x.
As mentioned in the introduction, TSMC’s N3 will follow on a 2.5-year cadence in the first half of 2023, as TSMC’s last FinFET node. While TSMC itself calls it a full-node shrink, no reasonable analysis could really describe it as such. Logic density scaling decreases further to just 1.7x, while SRAM will only see a 1.2x improvement. Analog will hardly shrink at all.
Intel’s analysis half a decade ago showed that SRAM and analog comprise 40-50% of Apple’s chips, so a real-world density of no more than 50% should be expected despite a 2.5-year cadence.
The newest information concerns N2. This node will move to GAAFET or MBCFET. TSMC intends to start risk production in the second half of 2023. This implies a two-year cadence compared to N3.
Given that risk production lags volume by approx. 12 months, and given that volume production lags product introduction by ca. 6 months (for example, N5 risk production started in H1’19, followed by the iPhone 12 launch 18 months later), this implies TSMC’s N2 gate-all-around will enter the market in the first half of 2025.
Intel: 7nm, 5nm Intel launched its 10nm in the second half 2020, and recently followed this up with 10nm SuperFin, which Intel claimed delivers the same benefits as a full-node jump would provide, in power and performance. (Obviously not in density.)
Intel announced in July 2020 it would shift its 7nm ramp by 6 to 12 months, which means volume availability is shifting from 2022 to 2023. While specifications of 7nm aren’t known yet, Intel has previously indicated it would be 2.0x or 2.4x shrink: at 200-240MT, it could be a fair bit denser than TMSC N5. It will still be a FinFET.
In June, Intel’s CTO confirmed however that Intel would make the transition to GAAFET “within the next five years”. The only process node that could fulfill this promise is 5nm. Taken at face value, this means at worst Intel will introduce GAAFET and 5nm in 2025, on par with TSMC. Intel has also said 5nm would be a 2x shrink.
Q: Can you give us the timeline for the introduction of nanoribbon/nanowire process technology into high volume production?
A: This is not a roadmap talk, so I'll be vague and say within in the next five years.
問：您能否給我們提供將nanoribbon/nanowire工藝技術引入大批量生產的時間表？
答：這不是路線圖討論，所以我會含糊地說說在未來五年內。
However, Intel’s roadmap is more aggressive than 2025. Intel announced in 2019 (before the 7nm delay) that it intended to go back to a 2-year cadence. A roadmap until 2029 also confirmed this. Given that 7nm was supposed to enter the market in Q4’21, this implied 5nm would launch in Q4’23, which Murthy confirmed:
- Excited about 5 and what they plan to deliver, well into development - On track for 2023 (2-2.5 year cadence) - Talked a lot about while they will be improving transistor performance, power etc that Interconnect is also a big factor
Under the assumption that 5nm is now also shifting by 6 to 12 months (even though a 7nm defect mode should have no impact whatsoever on 5nm development, in principle), this still implies that 5nm will launch in 2024, up to a year ahead of TSMC.
Some may say that Intel may not fulfill its roadmap, but this article is treating each vendor’s roadmap equally unless proven otherwise.
有人可能會說英特爾可能無法實現其路線圖，但是除非另外證明，否則本文將平等對待每 個供應商的路線圖。
Intel vs. TSMC Intel’s 10nm process has a standardized (which means the comparison is apples-to-apples) density of 100MT. While it obviously can’t be known how large the A14 would be on Intel’s 10nm process (and its resulting real-world density), in the past Apple’s SoC usually followed this standardized density metric fairly well, which makes the seemingly low 134MT of the A14 especially noteworthy.
So assuming that the A14 would achieve 100MT on Intel’s 10nm process, this suggests that in real-world density, TSMC may be just 1.35x ahead of Intel. That is more akin to a half-node advantage compared to a full-node leap.
因此，假設A14在Intel的10nm工藝上將達到100MT，這表明在實際密度下，TSMC可能僅比 Intel高1.35倍。與全節點的飛躍相比，這更類似於半節點的優勢。 (我自己不以為這樣是apples to apples)
In other words, Intel may be not as much behind as many would assume. Conversely, TSMC may also not be ahead as much would assume. Indeed, what Intel may lack in density, it may make up for in other areas in transistor (and packaging) technology, which it highlighted with its SuperFin technology (and Lakefield 3D stacking).
Similarly, if N3 only improves density by another 50%, it may only achieve closer to 200MT than the theoretical 300MT, which again might be closer to Intel’s 7nm than 5nm.
To validate this claim, more data about die sizes and transistors counts from multiple chips should be required from both Intel and TSMC, but Intel stopped releasing transistor counts around 2014: Intel argued that since its chips had a vastly different composition in terms of logic cells, I/O and SRAM (see image above), that any comparisons to Apple's transistor counts were misleading. In other words, all of Intel's CPUs have a markedly lower full-chip density than the standardized density. 為了證實這一說法，英特爾和台積電都需要更多有關多個晶片的晶片尺寸和晶體管數的數 據，但英特爾在2014年左右停止發布晶體管數：英特爾認為，由於其芯片在邏輯單元方面 存在很大差異，I / O和SRAM（請參見上圖），與Apple晶體管數量的任何比較都具有誤導 性。換句話說，所有英特爾CPU的全芯片密度均明顯低於標準密度。 (這就是為什麼我不認為是apples to apples, 至少不能拿理論去比實際混成的SOC)
Samsung Samsung is currently ramping its 5nm process. Samsung has made some efforts this year to assure press and investors that its 5nm process was not having yield issues, contrary to various reports.
Samsung’s 5nm is not a new node, but a direct derivative of its 7nm platform. As such, its density improvement will be even less than TSMC’s N5, and should be not much higher than Intel’s 10nm.
Samsung’s 3nm node will mark its next big step, and as Samsung has announced long ago, will mark its introduction of MCBFET, an industry-first. The node seems to be delayed somewhat, as it now targeted for 2022 volume production (compared to late 2021 previously). Samsung further claims a 0.65x or 0.55x shrink, which should put it around the density of TSMC’s 5nm rather than 3nm.
Still, as discussed TSMC’s N3 will be more like half-node shrink, so what Samsung may lack in density, it may make up in technology and time to market – not unlike Intel.
In that regard, Samsung’s early introduction of GAAFET will be similar to Intel’s FinFET at 22nm, as the latter was comparable in density to TSMC’s planar 28nm. While Samsung won’t hold a density advantage, it will still be ahead of TSMC by up to three years, and ahead of Intel by up to two years in introducing this technology in the market. In any case, Samsung already announced in 2019 it is intending to invest over $100 billion this decade to catch up to TSMC.
Takeaway TSMC, currently seen as the market leader, may lose its process technology leadership by 2024 or sooner.
結論 目前被視為市場領導者的台積電可能會在2024年或更早之前失去其工藝技術的領導地位。
The FinFET transistor, introduced in 2012 by Intel several years ahead of the rest of the industry (as one example of how relatively quick things can change), is running out of steam. As such, it has to be replaced by the GAAFET. While this transition won’t be as drastic as the initial change to FinFET was, it nevertheless is a major one. Just like the FinFET, it will mark the start of a new era of process technology and chip design.
This means that vendors who may have falling during the FinFET, may have an opportunity to catch up. Indeed, current data suggests TSMC will be the last vendor make this transition, up to one year behind Intel and three years behind Samsung.
Given the slowing of for example SRAM density scaling and the introduction of 3D logic stacking, and other unknows, the introduction of GAAFETs may perhaps be seen as a (more) reliable indicator of process technology leadership going forward, which I previously already argued is more than just transistor density: Intel Vs. TSMC: Process Technology Leadership Is More Than Transistor Density (NASDAQ:INTC).
In the past, Samsung has already served as the foundry for Apple, Nvidia (NVDA) and Qualcomm (QCOM) among others. So Samsung's differentiated GAAFET roadmap could have real foundry market share implications, while Intel continues to recover from its 10nm and 7nm delays seeking to regain process leadership.
intel製程演進 在 [情報] TSMC製程將於2024落後Intel和三星- 看板PC_Shopping 的美食出口停車場
來自國外老Intel人的分析
基於某些事實
2023量產7nm相當TSMC 5nm
GAAFET是更先進的製程技術
Intel最多讓C52等四年就能重返農藥(咦?
愛用三星的老黃
那精妙如達文西手術的刀法或將重出江湖
原文連結:
https://reurl.cc/OqNZDA
TSMC To Fall Behind Both Intel, Samsung By 2024
Summary
TSMC is currently seen as the most advanced semiconductor company, a position
it inherited from Intel due to latter’s 3-year 10nm delay.
However, a recent report indicates that TSMC will only move to
gate-all-around (GAA) transistors in 2025.
This will readily trail Samsung’s 2022 as well as Intel’s 2024 introduction
of GAAFETs.
This means TSMC could go from first to third within the next four years.
概要
台積電目前被視為最先進的半導體公司，由於英特爾3年的10nm延遲，它從英特爾那裡繼
承了這一地位。
然而，最近的一份報告表明，台積電將在2025年才採用GAAFET製程技術。
這將緊隨三星在2022年以及英特爾在2024年推出GAAFET之後。
這意味著台積電在未來四年內可能會從第一掉到第三。
Overview
TSMC (TSM) is currently widely seen as the leader in semiconductor
technology. However, this is not something it achieved by doing anything
noteworthy: TSMC inherited this status from Intel (INTC) as the latter took
five years to launch its first 10nm product, whereas Moore’s Law calls for a
two-year cadence. TSMC did nothing but continue to adhere to said cadence.
總覽
台積電（TSM）目前被廣泛視為半導體技術的領導者。但是，這並不是通過做任何值得注
意的事情來實現的：台積電從英特爾（INTC）繼承了這一地位，因為後者花了五年時間才
推出了其首款10nm產品，而摩爾定律則要求兩年的節奏。台積電什麼也沒做，只是繼續遵
守上述節奏。(譯注:在講龜兔賽跑, Intel沒輸, 只是在睡覺...)
Indeed, in an article early this year (and that admittedly has become
outdated since Intel announced its 7nm delay), I already noted that TSMC
itself was not particularly moving fast, also falling behind the Moore’s Law
curve: TSMC was transitioning from 5nm (N5) to 3nm (N3) on a
longer-than-usual 2.5-year cadence, while also increasing density by much
less than the 2.0x Moore’s Law calls for: for example, SRAM density will
only improve by a meager 1.2x. (So at the time, I noted that this gave Intel
an opportunity to catch up, but Intel subsequently delayed its 7nm, which
previously was intended to allow Intel to move on quickly from its plagued
10nm node.)
確實，在今年年初的一篇文章中（自英特爾宣布7nm延遲以來，這已經過時了），我已經
指出，台積電本身並沒有特別快地發展，也落後於摩爾定律曲線：台積電正在從5nm（N5
）過渡）到3nm（N3）的速度比通常的2.5年更長，而密度的增加也遠少於摩爾定律所要求
的2.0倍：例如，SRAM密度僅提高了1.2倍。（因此，當時我注意到這給了英特爾一個追趕
的機會，但英特爾隨後推遲了其7納米製程，這以前是為了使英特爾能夠從受困的10nm
節點上迅速發展。）
Recently, the first report about 2nm (N2) has arrived. As expected, this will
mark TSMC’s transition from the FinFET transistor, first introduced by Intel
in 2012 before being adopted by TSMC in 2015, to the gate-all-around
transistor or GAAFET. Notably, TSMC is slated to move back to 2-year cadence,
which implies an early 2025 market introduction of N2, after a decade of
FinFET.
最近，有關2nm（N2）的第一份報告已經到來。正如預期的那樣，這將標誌著台積電從
FinFET晶體管過渡到gate-all-around FET或GAAFET.(FinFET晶體管由英特爾於2012年首次
引入，然後於2015年由台積電採用。)值得注意的是，台積電計劃將回歸兩年製程，這意味
著在使用FinFET十年之後，N2將於2025年初進入市場。
The issue with this is that TSMC’s two remaining leading edge competitors,
Samsung and Intel, are both scheduled to move to the GAAFET ahead of TSMC.
This means that TSMC could go from first to third by 2024.
問題在於，台積電剩下的兩個領先的競爭對手三星和英特爾都計劃在台積電之前遷移到
GAAFET。這意味著台積電到2024年可能會從第一落到第三。
For investors, that means they should not assume TSMC is the last foundry
standing to pursue Moore’s Law, as competition is set to intensify.
對於投資者來說，這意味著他們不應該認為台積電是追求摩爾定律的最後一家半導體工廠
，因為競爭將加劇。
Terminology
I use GAAFET (gate-all-around) as the general term for a transistor whose
gate surrounds all four sides of the channel. A FinFET surrounds three sides,
and a planar one only one side.
術語
我將GAAFET（gate-all-around）用所有四面環繞閘極的晶體管的代稱。FinFET圍繞三個側
面，而平面僅一個側面。
Samsung mostly uses the term MCBFET (multi-channel bridge) or nanosheet.
三星通常使用術語MCBFET或nanosheet。
Samsung differentiates this from a nanowire, which as the name suggests is
more like a wire than sheet of paper, in terms of geometry.
三星將其與nanowire區分開來，顧名思義，nanowire就幾何而言更像是線而不是紙。
A last name, mostly used by Intel, is nanoribbon. From the pictures from
Intel's research, this seems similar to a nanosheet, but perhaps it is a bit
in between both.
Inte主要使用nanoribbon。從英特爾研究的圖片來看，這似乎與nanosheet相似，但可能介
於兩者之間。
Lastly, node names: TSMC uses Nx, while Samsung and Intel continue to use xnm.
最後，節點名稱：TSMC使用Nx，而Samsung和Intel繼續使用xnm。
TSMC: N5, N3, N2
As widely known, TSMC has moved to N5 in the second half of 2020, at a
two-year cadence compared to N7. However, initial findings suggest that while
the cadence is on par with Moore’s Law, the shrink is not. In particular,
the Apple (AAPL) A14 only achieved a density of 134MT (133 million transistor
per mm2). This represent an increase of just 49% compared to 90MT on the A13.
台積電：N5，N3，N2
眾所周知，台積電已於2020年下半年遷移到N5，與N7相比，以兩年的節奏發展。但是，初
步發現表明，雖然節奏與摩爾定律相當，但收縮率卻沒有。特別是，Apple（AAPL）A14僅
實現了134MT的密度（每平方毫米1.33億個晶體管）。與A13的90MT相比，這僅增長了49％
。
This compares to TSMC’s claim of a 1.8x shrink with N5, which would result
in a standardized density of 170MT. This lower shrink achieved by Apple can
be attributed for a large part due to the much lower SRAM (memory) shrink of
just 1.3x.
相比之下，台積電聲稱N5的收縮率是1.8倍，這將導致標準密度為170MT。蘋果實現的這種
較低的收縮在很大程度上可以歸因於SRAM（快取記憶體）的收縮率低得多，僅為1.3倍。
As mentioned in the introduction, TSMC’s N3 will follow on a 2.5-year
cadence in the first half of 2023, as TSMC’s last FinFET node. While TSMC
itself calls it a full-node shrink, no reasonable analysis could really
describe it as such. Logic density scaling decreases further to just 1.7x,
while SRAM will only see a 1.2x improvement. Analog will hardly shrink at all.
如導言所述，作為台積電的最後一個FinFET節點，台積電的N3將於2023年上半年遵循2.5
年的節奏。雖然台積電本身稱其為全節點收縮，但沒有任何合理的分析可以真正描述它。
邏輯密度縮放比例進一步降低至1.7倍，而SRAM僅提高1.2倍。模擬量幾乎不會收縮。
Intel’s analysis half a decade ago showed that SRAM and analog comprise
40-50% of Apple’s chips, so a real-world density of no more than 50% should
be expected despite a 2.5-year cadence.
英特爾十年前的分析表明，SRAM和類比晶片佔Apple晶片的40-50％，因此，儘管有2.5年
的節奏，但現實世界中的密度預計不會超過50％。
The newest information concerns N2. This node will move to GAAFET or MBCFET.
TSMC intends to start risk production in the second half of 2023. This
implies a two-year cadence compared to N3.
在最新的信息涉及N2。該節點將移至GAAFET或MBCFET。台積電計劃在2023年下半年開始風
險生產。與N3相比，這意味著兩年的節奏。
Given that risk production lags volume by approx. 12 months, and given that
volume production lags product introduction by ca. 6 months (for example, N5
risk production started in H1’19, followed by the iPhone 12 launch 18 months
later), this implies TSMC’s N2 gate-all-around will enter the market in the
first half of 2025.
鑑於這種風險，生產滯後量約。大約12個月，並且考慮到批量生產落後於產品推出的時間
。6個月（例如，N5風險生產於19年上半年開始，隨後iPhone 12於18個月後推出），這意
味著台積電的N2 GAAFET將在2025年上半年進入市場。
Intel: 7nm, 5nm
Intel launched its 10nm in the second half 2020, and recently followed this
up with 10nm SuperFin, which Intel claimed delivers the same benefits as a
full-node jump would provide, in power and performance. (Obviously not in
density.)
英特爾：7nm，5nm
英特爾於2020年下半年推出了10nm技術，最近又推出了10nm SuperFin技術，英特爾聲稱
該技術在功耗和性能方面可提供與全節點躍遷相同的優勢。（顯然不是密度。）
Intel announced in July 2020 it would shift its 7nm ramp by 6 to 12 months,
which means volume availability is shifting from 2022 to 2023. While
specifications of 7nm aren’t known yet, Intel has previously indicated it
would be 2.0x or 2.4x shrink: at 200-240MT, it could be a fair bit denser
than TMSC N5. It will still be a FinFET.
英特爾在2020年7月宣布將其7nm的升級時間推遲6到12個月，這意味著批量供貨時間將從
2022年轉移到2023年。雖然尚不知道7nm的規格，但英特爾之前曾表示它將是2.0倍或2.4
倍。收縮：在200-240MT時，它可能比TMSC(原文錯字) N5密度高一點。它將仍然是FinFET
。
(譯註: TSMC 5nm為171.3MT)
In June, Intel’s CTO confirmed however that Intel would make the transition
to GAAFET “within the next five years”. The only process node that could
fulfill this promise is 5nm. Taken at face value, this means at worst Intel
will introduce GAAFET and 5nm in 2025, on par with TSMC. Intel has also said
5nm would be a 2x shrink.
然而，6月，英特爾首席技術官確認英特爾將在“未來五年內”過渡到GAAFET。可以滿足
這一承諾的唯一工藝節點是5nm。從表面上看，這意味著最壞的情況是，英特爾將在2025
年推出GAAFET和5nm，與TSMC持平。英特爾也曾表示，5nm將密度增加2倍。
Q: Can you give us the timeline for the introduction of nanoribbon/nanowire
process technology into high volume production?
A: This is not a roadmap talk, so I'll be vague and say within in the next
five years.
問：您能否給我們提供將nanoribbon/nanowire工藝技術引入大批量生產的時間表？
答：這不是路線圖討論，所以我會含糊地說說在未來五年內。
However, Intel’s roadmap is more aggressive than 2025. Intel announced in
2019 (before the 7nm delay) that it intended to go back to a 2-year cadence.
A roadmap until 2029 also confirmed this. Given that 7nm was supposed to
enter the market in Q4’21, this implied 5nm would launch in Q4’23, which
Murthy confirmed:
但是，英特爾的路線圖比2025年更具侵略性。英特爾在2019年（延遲7nm製程之前）宣
布，打算恢復為2年的節奏。直到2029年的路線圖也證實了這一點。考慮到7nm應該在21年
第4季度進入市場，這意味著5nm將在23年第4季度推出，Murthy確認：
Comments on 5nm from Murthy:
- Excited about 5 and what they plan to deliver, well into development
- On track for 2023 (2-2.5 year cadence)
- Talked a lot about while they will be improving transistor performance,
power etc that Interconnect is also a big factor
Under the assumption that 5nm is now also shifting by 6 to 12 months (even
though a 7nm defect mode should have no impact whatsoever on 5nm development,
in principle), this still implies that 5nm will launch in 2024, up to a year
ahead of TSMC.
假設5nm現在也要轉變6到12個月（即使從原理上講7nm缺陷模式不會對5nm的發展產生任何
影響），這仍然意味著5nm將在2024年推出，比台積電提前一年。
Some may say that Intel may not fulfill its roadmap, but this article is
treating each vendor’s roadmap equally unless proven otherwise.
有人可能會說英特爾可能無法實現其路線圖，但是除非另外證明，否則本文將平等對待每
個供應商的路線圖。
Intel vs. TSMC
Intel’s 10nm process has a standardized (which means the comparison is
apples-to-apples) density of 100MT. While it obviously can’t be known how
large the A14 would be on Intel’s 10nm process (and its resulting real-world
density), in the past Apple’s SoC usually followed this standardized density
metric fairly well, which makes the seemingly low 134MT of the A14 especially
noteworthy.
英特爾對上台積電
英特爾的10nm製程的標準密度為100MT（這意味著同樣標準之間的比較）。雖然顯然無法知
道A14在Intel的10nm工藝上將有多大（及其最終的實際密度），但在過去，Apple的SoC通
常都很好地遵循了這種標準化的密度度量標準，這使得似乎低至134MT的A14特別值得注意
。(這是在說實際混和了SRAM和各種晶片的N5 A14 SOC密度有點低)
So assuming that the A14 would achieve 100MT on Intel’s 10nm process, this
suggests that in real-world density, TSMC may be just 1.35x ahead of Intel.
That is more akin to a half-node advantage compared to a full-node leap.
因此，假設A14在Intel的10nm工藝上將達到100MT，這表明在實際密度下，TSMC可能僅比
Intel高1.35倍。與全節點的飛躍相比，這更類似於半節點的優勢。
(我自己不以為這樣是apples to apples)
In other words, Intel may be not as much behind as many would assume.
Conversely, TSMC may also not be ahead as much would assume. Indeed, what
Intel may lack in density, it may make up for in other areas in transistor
(and packaging) technology, which it highlighted with its SuperFin technology
(and Lakefield 3D stacking).
換句話說，英特爾可能沒有很多人想像的落後。反過來說，台積電也可能不如預期的那樣
領先。確實，英特爾可能缺乏密度，但它可能會在晶體管（和封裝）技術的其他領域得到
彌補，而英特爾在其SuperFin技術（以及Lakefield 3D堆棧）中強調了這一點。
Similarly, if N3 only improves density by another 50%, it may only achieve
closer to 200MT than the theoretical 300MT, which again might be closer to
Intel’s 7nm than 5nm.
同樣，如果N3僅將密度提高50％，則只能實現比理論上的300MT更接近200MT的水平，後者
又可能比5nm更接近英特爾的7nm。
To validate this claim, more data about die sizes and transistors counts from
multiple chips should be required from both Intel and TSMC, but Intel stopped
releasing transistor counts around 2014: Intel argued that since its chips
had a vastly different composition in terms of logic cells, I/O and SRAM (see
image above), that any comparisons to Apple's transistor counts were
misleading. In other words, all of Intel's CPUs have a markedly lower
full-chip density than the standardized density.
為了證實這一說法，英特爾和台積電都需要更多有關多個晶片的晶片尺寸和晶體管數的數
據，但英特爾在2014年左右停止發布晶體管數：英特爾認為，由於其芯片在邏輯單元方面
存在很大差異，I / O和SRAM（請參見上圖），與Apple晶體管數量的任何比較都具有誤導
性。換句話說，所有英特爾CPU的全芯片密度均明顯低於標準密度。
(這就是為什麼我不認為是apples to apples, 至少不能拿理論去比實際混成的SOC)
Samsung
Samsung is currently ramping its 5nm process. Samsung has made some efforts
this year to assure press and investors that its 5nm process was not having
yield issues, contrary to various reports.
三星
三星目前正在加快其5nm製程。與各種報導相反，三星今年已做出一些努力向媒體和投
資者保證其5nm製程沒有產量問題。
Samsung’s 5nm is not a new node, but a direct derivative of its 7nm
platform. As such, its density improvement will be even less than TSMC’s N5,
and should be not much higher than Intel’s 10nm.
三星的5nm並不是一個新節點，而是其7nm平台的直接衍生產品。這樣，它的密度改進將甚
至不及台積電的N5，也不應高於英特爾的10nm。
Samsung’s 3nm node will mark its next big step, and as Samsung has announced
long ago, will mark its introduction of MCBFET, an industry-first. The node
seems to be delayed somewhat, as it now targeted for 2022 volume production
(compared to late 2021 previously). Samsung further claims a 0.65x or 0.55x
shrink, which should put it around the density of TSMC’s 5nm rather than 3nm.
三星的3nm節點將標誌著其下一步發展，正如三星很久以前宣布的那樣，它將標誌著其業
界首創MCBFET的推出。該節點似乎有所延遲，因為它現在的目標是2022年的量產（之前是
2021年末）。三星進一步聲稱縮小了0.65倍或0.55倍，這應該使其接近TSMC 5nm而不是
3nm的密度。
Still, as discussed TSMC’s N3 will be more like half-node shrink, so what
Samsung may lack in density, it may make up in technology and time to market
– not unlike Intel.
不過，正如所討論的台積電N那樣3將更像是半節點收縮，因此三星可能密度不太增加
，它可能會在技術和上市時間上有所彌補-與英特爾不同
In that regard, Samsung’s early introduction of GAAFET will be similar to
Intel’s FinFET at 22nm, as the latter was comparable in density to TSMC’s
planar 28nm. While Samsung won’t hold a density advantage, it will still be
ahead of TSMC by up to three years, and ahead of Intel by up to two years in
introducing this technology in the market. In any case, Samsung already
announced in 2019 it is intending to invest over $100 billion this decade to
catch up to TSMC.
在這方面，三星早期推出的GAAFET與22nm的Intel FinFET相似，因為後者的密度可與台積
電的平面28nm相媲美。雖然三星將不會擁有密度優勢，但在市場上推出這項技術的領先地
位仍然領先於TSMC三年，領先於Intel兩年。無論如何，三星已經在2019年宣布它將計劃
在這十年內投資超過1000億美元以趕上台積電。
Takeaway
TSMC, currently seen as the market leader, may lose its process technology
leadership by 2024 or sooner.
結論
目前被視為市場領導者的台積電可能會在2024年或更早之前失去其工藝技術的領導地位。
The FinFET transistor, introduced in 2012 by Intel several years ahead of the
rest of the industry (as one example of how relatively quick things can
change), is running out of steam. As such, it has to be replaced by the
GAAFET. While this transition won’t be as drastic as the initial change to
FinFET was, it nevertheless is a major one. Just like the FinFET, it will
mark the start of a new era of process technology and chip design.
英特爾在2012年推出了FinFET晶體管，該晶體管在同行業中比其他行業領先了幾年（這是
事物可以相對快速地變化的一個例子），但這種晶體管已經用盡了。因此，必須用GAAFET
代替它。雖然這種轉變不會像FinFET最初的轉變那樣劇烈，但它是一個重大的轉變。就像
FinFET一樣，它將標誌著製程技術和芯片設計新時代的開始。
This means that vendors who may have falling during the FinFET, may have an
opportunity to catch up. Indeed, current data suggests TSMC will be the last
vendor make this transition, up to one year behind Intel and three years
behind Samsung.
這意味著可能在FinFET期間跌落的供應商可能有機會追趕。確實，目前的數據表明，台積
電將是最後一次實現這一轉變的廠商，比英特爾落後了一年，三星落後了三年。
Given the slowing of for example SRAM density scaling and the introduction of
3D logic stacking, and other unknows, the introduction of GAAFETs may perhaps
be seen as a (more) reliable indicator of process technology leadership going
forward, which I previously already argued is more than just transistor
density: Intel Vs. TSMC: Process Technology Leadership Is More Than
Transistor Density (NASDAQ:INTC).
考慮到SRAM密度縮放的放慢和3D邏輯堆棧的引入以及其他一些未知因素，GAAFET的引入可
能被視為工藝技術領先地位的（更可靠）指示，我之前已經指出過不僅僅是晶體管密度：
IntelVs。台積電（TSMC）：工藝技術的領導地位遠勝於晶體管密度（納斯達克：INTC）
。
(大哥沒有輸, 技術上)
In the past, Samsung has already served as the foundry for Apple, Nvidia
(NVDA) and Qualcomm (QCOM) among others. So Samsung's differentiated GAAFET
roadmap could have real foundry market share implications, while Intel
continues to recover from its 10nm and 7nm delays seeking to regain process
leadership.
過去，三星曾擔任Apple，Nvidia（NVDA）和Qualcomm（QCOM）等公司的代工廠。因此，
三星差異化的GAAFET路線圖可能會對晶圓代工市場產生實際影響，而英特爾繼續從其10nm
和7nm延遲中恢復過來，以尋求重新奪回工藝領先地位。
--
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